Verification of Fault Analysis Using I Test Methodology in CMOS OP-AMP DDQ

In earlier Fault Analysis (FA) has been exploited for several aspects of analog testing. These include, test development, DfT schemes qualification and fault grading. In present, I testing has become a widely DDQ accepted defect detection technique in CMOS ICs.In this paper we described I testing technique for DDQ analyzing physical faults. A two stage CMOS opamp is taken as Circuit Under Test (CUT) and it is analyzed for verification. Testability has been enhanced in the testing procedure using a simple fault injection technique. The faults have been diagnosed by building a Build in current Sensor (BISC). This I test method makes the DDQ testing method easy to analyze the fault such as open and short of the CMOS transistor. In previous method few faults were injected using fault injection technique and it has been tested. When compare to previous method, more faults were injected in Circuit under test and it has been analyzed one by one. It has been inferred that we have minimized the probability of input vectors to the circuit under test in I test method. From the DDQ result it is concluded that only 33.3% of the circuit is enough to apply I test. It is due to the capacitance and DDQ other parameters present in the CUT. This capacitance effect on I test was also analyzed. The simulated DDQ result confirms the functionality of the proposed test method.